In 2008, the superlattice State Key Laboratory of the Institute of Semiconductors, Chinese Academy of Sciences successfully developed the Journal of Solid State Circuits (JSSC), 1470 (2008), which integrates pixels and processing units. The chip has the function of full pixel parallel visual information processing, can complete low-level and intermediate visual image processing based on mathematical morphology methods, and can achieve high-speed target tracking and image feature extraction.http://www.ic-bom.com/

With the support of the National Natural Science Foundation of China, the Ministry of Science and Technology, and the Chinese Academy of Sciences, in the past two years, researcher Wu Nanjian and doctoral students Zhang Wancheng and Fu Qiuyu from the Semiconductor Institute have continued to conduct in-depth research and successfully developed a new visual chip. This chip has the architectural feature of separating image sensor pixel array and processing unit array circuits, integrating three types of processors with different degrees of parallelism: two-dimensional processing unit array, one-dimensional row parallel processor array, and embedded microprocessor, respectively, to achieve primary, intermediate, and high-level image processing functions. Successfully solved the contradiction between image resolution, processing function, processing speed, and chip area, and achieved complex advanced image processing functions such as high-speed image recognition on the chip, laying a solid foundation for the future application of visual chips in fields such as high-speed target tracking, robot vision, and fast image recognition.